1. Field of the Invention
This invention relates generally to semiconductor memory devices having improved error correcting circuits, and more particularly to testing circuits for memory cells which are used for correction of an error.
2. Description of the Background Art
In recent years, the capacity of a semiconductor memory device has been increased remarkably by a high integration technique. As such integration proceeds, memory cells are likely to be defective. As countermeasure for defective memory cells produced in the other good memory cells, two methods are conventionally known, including a method which employs a redundancy circuit and another method which makes use of an error correcting circuit (hereinafter referred to as ECC). An ECC will be described in the following.
An ECC is provided in a semiconductor memory device such as, for example, an erasable programmable read-only memory device (hereinafter referred to as EPROM) in order to assure a high degree of reliability on data stored in the semiconductor memory device. An EPROM to which an ECC is applied includes memory cells for the ECC in addition to memory cells for storage of data. In the case of, for example, single bit error correction (SEC), where the bit length of a data word is m and the bit length of an additional word for the ECC is k, it is required for m and k to satisfy the following inequality: EQU 2.sup.k -1 .gtoreq.m+k (1)
Combinations of such data bit lengths m and ECC bit lengths k which present integers are determined in accordance with the expression (1) above. The results are shown in Table 1 below.
TABLE 1 ______________________________________ Data Bit Length (m) 4 8 16 32 64 ECC Bit Length (k) 3 4 5 6 7 ______________________________________
FIG. 6 shows in a block diagram a conventional semiconductor memory device to which an ECC is applied. Referring to FIG. 6, the semiconductor memory device shown includes a plurality of memory cells 52 for storing data therein, ECC memory cells 62 for storing error correcting codes therein, a circuit 51 for reading stored data out of the memory cells 52 and for writing data into the memory cells 52, a circuit 61 for reading stored data out of the memory cells 62 and for writing data into the memory cells 62, an error detecting circuit 2, an error correcting circuit 3, a converting circuit for the ECC, and a control circuit 94 for the circuits listed above. Inputting and outputting of data are executed by way of a data inputting/outputting circuit 4.
FIG. 7 shows, in a circuit diagram, exemplary details of the circuits 1, 2 and 3 (hereinafter referred to as error correcting circuit section) shown in FIG. 6. In the circuit construction shown, the data bit length m is m=4 and the ECC bit length k is k=3 for simplification of explanation. In addition, in FIG. 7, the data reading/writing circuit 51 and the data storage cells 52 shown in FIG. 6 are shown as a single memory circuit 50 in a simplified form while the ECC reading/writing circuit 61 and the ECC storage memory cells 62 are shown as another single memory circuit 60.
Referring to FIG. 7, an ECC converting circuit 1 includes three exclusive OR (EXOR) gates 11 to 13 connected to receive data D0 to D3 from the data inputting/outputting circuit. The ECC memory circuit 60 is connected to receive data D0 to D3. The error detecting circuit 2 includes three gates 21 to 23 individually connected to receive output signals of the memory circuits 50 and 60 for individual bits. The error correcting circuit 3 includes four AND gates 33 to 36 connected to receive output signals of the error correcting circuit 2, three inverters 30 to 32, and further four EXOR gates 37 to 40 connected to receive signals from the AND gates 33 to 36 and the memory circuit 50. Output data signals Q0 to Q3 with which errors have been corrected by the error correcting circuit 3 are delivered by way of the EXOR gates 37 to 40.
Subsequently, operation for error correction will be described. In the example shown in FIG. 7, i-th data word di0 to di3 constituted from four bits D0 to D3 is written into the memory circuit 50. The i-th data word here denotes a word stored in or to be stored into memory cells designated by a pair of decoders 92 and 93 in response to an address signal Ai. Meanwhile, the EXOR gates 11 to 13 send output signals thereof to the memory circuit 60 in response to the data signals D0 to D3. The memory circuit 60 receives the output signals and stores them as an ECC word ci0 to ci2.
Commonly, an EXOR gate provides an output signal "0" in response to an even number of input signal or signals "1". To the contrary, an EXOR gate provides an output signal or signals "1". Accordingly, ECC word data specified by the EXOR gates 11 to 13 are stored into the ECC memory circuit 60 in response to the data signals D0 to D3.
When memory cells of the memory circuits 50 and 60 are normal, each of the EXOR gates 21 to 23 provides a signal "0" in response to an even number of input signal or signals "1". To the contrary, when there is some defect or abnormality with memory cells of the memory circuits 50 and 60, and particularly when one bit error takes place (i.e., when an error takes place only with a bit of word), one of the EXOR gates 21 to 23 provides an output signal "1". In the error correcting circuit 3, one of data di0 to di3 delivered from the memory circuit 50 is corrected by the EXOR gates 37 to 40 in response to the output signal "1" delivered from the one of the EXOR gates 21 to 23. As a result, data Q0 to Q3 with which the error has been corrected are delivered from the error correcting circuit 3.
Subsequently, description will be given of an example of data. For example, it is assumed that data (D3, D2, D1, D0) are (0, 0, 1, 0), respectively. In this instance, the data (0, 0, 1, 0) are stored as an i-th data word (di3, di2, di1, di0) into the memory circuit 50. Meanwhile, data (1, 0, 1) are stored as an ECC word (ci2, ci1, ci0) into the memory circuit 60 in response to the data D0 to D3.
When the memory cells of the memory circuits 50 and are normal, all of the EXOR gates 21 to 23 deliver an output signal "0". Consequently, all of the AND gates 33 to 36 provide an output signal "0" as a result, the EXOR gates 37 to 40 output data signals Q0 to 3 which are specified by the data word di0 to di3.
Operation when there is some defect or abnormality in any of the memory cells of the memory circuit 50, for example, when the data di2 is changed in value from "0" to "1" due to some defect or abnormality of the memory cell in which the data di2 is stored will be such as follows. In this instance, data (0, 1, 1, 0) are stored as a data word (di3, di2, di1) di0) in the memory circuit 50. When they are stored, the EXOR gates 22 and 23 provide an output signal "1" in response to the data di2. As a result, the AND gate 35 provides an output signal "1" while the other AND gates 33, 34 and 36 deliver an output signal "0". Accordingly, the data di2 with which an error takes place is corrected by the EXOR gate 39 in response to the signal "1" delivered from the AND gate 35.
Where the circuit shown in FIG. 7 is applied, even if data is reversed from "1" to "0" due to some defect of a memory cell, detection and correction of the error of the data are accomplished in a similar manner. However, when an error takes place for two or more bits, a proper correcting operation cannot be achieved.
Generally, in order to perform an inspection or test of a semiconductor memory device, it is desirable that arbitrary data can be written into memory cells to be tested. With regard to the memory circuit 50 shown in FIG. 7, that is, with regard to the data storage memory cells 52 shown in FIG. 6, arbitrary data can be written as data D0 to D3 into it from the outside. However, no arbitrary data can be written into the memory circuit 60, that is, the ECC memory cells 62 shown in FIG. 6 because the ECC converting circuit 1 is provided at the preceding stage. In particular, since data to be written into the ECC memory cells 62 are determined by the EXOR gates 11 to 13 in the circuit 1 in response to data D0 to D3, no arbitrary data can be written into the ECC memory cells 62. Consequently, writing of a checker pattern or writing of data "0" into all of memory cells which is commonly performed in inspection of a semiconductor memory cannot be accomplished readily. In addition, when written test data are read out, it is difficult to determine whether or not the ECC memory cells 62 are normal.